TSMC’s N4X Technologies Targets HPC

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New process technologies unveiled by Taiwan Semiconductor Production Co. is geared toward superior-general performance computing (HPC) workloads and units. The foundry large stated its N4X process technologies is scheduled for demo generation for the duration of the initial 50 percent of 2023.

The new processing node is TSMC’s initially foray into the growing HPC market. NX4 targets designs with transistors as tiny as 5 nm, delivering a claimed 15-p.c overall performance raise when compared to its N5 procedures. TSMC also statements the N4X presents a 4-% functionality enhancement around its N4P at 1.2 volts.

The firm earlier unveiled HPC method know-how based mostly on its N5A and N6RF technologies. The N4X style is an improvement of its N5A, enhancing on its functionality and most clock frequencies.

TMSC procedure technologies roadmap (Source: TMSC) (Click on picture to enlarge.)

The “X” denotes TSMC’s increasing thrust into the HPC chip layout sector, which the organization mentioned is among its speediest increasing business segments.

TSMC’s third-quarter earnings report showed a financial gain of NT$156.26 billion (U.S.$5.56 billion), up 13.8 % when compared to last calendar year. The organization attributed the income raise to enhanced need in its four advancement platforms, like smartphones, IoT, automotive programs and HPC. It expects approach systems aimed at HPC to carry on offering development into 2022.

“The calls for of the HPC section are unrelenting, and TSMC has not only personalized our ‘X’ semiconductor systems to unleash top overall performance but has also combined it with our 3DFabric,” reported Kevin Zhang, TSMC’s senior vice president of enterprise development.

Yujun Li, TSMC’s director of HPC organization development, included that N4X can handle an raise in computing demand as HPC chips access their greatest reticle sizing.

“Our shoppers can increase the amount of primary-edge comput[ing] chips for utmost compute electric power. Or, chips can be partitioned into a number of chiplets with each individual adopting the optimum know-how of alternative – logic optimized, IO and analog optimized or memory optimized.”

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